The present invention relates to a data buffer providing a means for enhancing the efficiency of data transfer to a memory and a coprocessor optimized for block-unit data transfer.
With recent enhancement in performance of microprocessors and the like, it has become necessary to provide a memory interface with high data transfer capability. There are two ways for improving the data transfer capability of a memory; increasing the bit width for data transfer and increasing the data transfer rate.
With size scale-down in semiconductor fabrication process, the memory capacity has increased. To improve the data transfer capability without increasing the holding memory amount, it is necessary to shorten the transfer cycle time while rather decreasing, not increasing, the bit width for the data transfer.
Under the circumstances described above, there have been developed memories such as SDRAMs and RDRAMs having a high-speed synchronous transfer capability exceeding 100 MHz and memory interfaces corresponding to such memories. These memories realize high-speed data transfer by accessing data with a large bit width inside the device, buffering data in data block units, and outputting data at continuous several to several tens of clocks. These memories therefore have a feature of being high in data transfer capability (throughput) but large in the time required from address input until access of first data of relevant block data (latency). This indicates that if such a memory intended for high-speed synchronous transfer frequently performs access of data having a size smaller than the block handled by the memory, the memory transfer capability decreases, and this will rather degrade the system performance.
To solve the above problem, the following measure is taken. Interfaces for SDRAMs and RDRAMs have a buffer memory appropriate to the block size of the corresponding memory. Using the buffer memory, continuous data accesses are put together into one when the addresses for the current data access and the next data access are continuous, to enhance the data transfer capability. However, this measure is effective only when the accesses accompanied by prefetch of instructions and data and the read/write operations by a DMA controller and the like are respectively continuous temporally. In general systems, instruction fetch, data access and DMA access compete with one another. Therefore, the above measure fails to provide an effect commensurate with the large-scale and complicate interface.
In view of the above, the problem to be solved by the present invention is to enhance the efficiency of data transfer in the case, for example, of transferring results of processing of media data and results of calculation of coordinates of image data to a coprocessor for graphics in digital TV sets and portable equipment.
The processing described above requires a large amount of data and a large scale of computation. Therefore, although the data transfer is directed to consecutive addresses when considered in a long time unit, it lacks in continuity when considered in a short time unit. Therefore, such data transfer fails to benefit from the effect of the memory interface described above having the measure of putting together a plurality of data accesses into one. Moreover, since write of the processing results largely delays, read of memory data required for new processing must wait. This further degrades the system performance.
An object of the present invention is providing a data buffer capable of enhancing the efficiency of data transfer from an operator such as a CPU to a memory and a coprocessor optimized for block-unit data transfer and thereby enhancing system performance.
To solve the problem described above, the present invention utilizes the points that the data in question will not be referred to by the same program after being written, and that the data is written to consecutive addresses but the write of the data is not continuous temporally. In other words, according to the present invention, there is provided a means for writing data into an input data register to which a unique address is allocated and putting together the written data into a data block of a predetermined transfer destination data size (N bytes; N=16, for example).
To state specifically, the first feature of the invention is to provide a data buffer including: an initial address register for holding a transfer destination address input via a data bus as an initial address; an input data register for holding maximum k pieces (k is an integer equal to or more than 2) of M-byte data (M is an integer equal to or more than 1) input via the data bus; an address decoder for decoding an address on an address bus so that the transfer destination address on the data bus is written into the initial address register if the address on the address bus is an address designating the initial address register and that the M-byte data on the data bus is written into the input data register if the address on the address bus is an address designating the input data register when a data buffer write signal is provided; an accumulated data size register for holding an accumulated data size representing the size of a data block of maximum N bytes (N=kM) accumulated in the input data register; an output data register for holding a data block to be transferred; a block address register for holding a head address of the data block to be transferred; a block size register for holding the block size representing the size of the data block to be transferred; a block address counter for setting the initial address transferred from the initial address register as an initial value and holding a block address updated according to the block size; and a sequence controller for updating the accumulated data size by M byte(s) every time the M-byte data on the data bus is written into the input data register, setting the block size in the block size register at N bytes if the initial address is an N-byte boundary address (an address divisible by N), waiting until the accumulated data size reaches N bytes, transferring the data block of N bytes accumulated in the input data register to the output data register, transferring the block address held by the block address counter to the block address register, asserting a block data write request signal so that the data block of N bytes held by the output data register is transferred, resetting the accumulated data size at 0, and updating the block address held by the block address counter by N bytes.
The second feature of the data buffer of the invention is that data transfer of a new block to a destination continuous from the previous destination is possible by writing data into the input data register without setting a new transfer destination address in the initial address register. This eliminates the necessity of designating the transfer destination is address every write of data into the data buffer, and thus enhances the data transfer efficiency.
The third feature of the data buffer of the invention is that the data buffer may be provided with a means for forcefully transferring data to a memory in the following manner. That is, when data of a size less than the block data size exists in the input data register at the time of setting of a transfer destination address in the initial address register, the entire existing data is swept out of the input data register as block data by assertion of the block data write request signal. With provision of this means, data can be forcefully transferred under software instruction in the case of transfer of data of which size is not a value obtained by multiplying the block size by an integer, for example.
The fourth feature of the invention is as follows. When a transfer destination address that is not at an N-byte boundary is designated, the block data write request signal may be asserted every write into the input data register until a byte boundary corresponding to the block size is reached. With this configuration, the data buffer can support a memory controller allowing only data transfer in 4-byte units in addition to the data transfer in 16-byte units and having no block transfer means in 8-byte units or 12-byte units in the case of N=16, for example.
The fifth feature of the data buffer of the invention is that when a transfer destination address other than an N-byte boundary address is designated, data up to a byte boundary corresponding to the block size may be put together as block data and the block data write request signal may be asserted. With this configuration, the data buffer can support a memory controller having a block transfer means allowing data transfers in 4-byte units, 8-byte units and 12-byte units in addition to the data transfer in 16-byte units in the case of N=16, for example, unlike the fourth feature described above, and thus optimum memory access is provided.
The sixth feature of the data buffer of the invention is that the data buffer can hold two or more blocks of block data, to provide buffering between the rate of write from the CPU and the block data transfer rate.
The seventh feature of the data buffer of the invention is that a signal for disabling write into the input data register may be generated if transfer to the memory controller and the like fails to catch up with the write into the data buffer. This prevents written data from being lost.